The Stratix® V field programmable gate array (FPGA) circuit manufactured by Altera Corporation of San Jose, Calif., includes a memory interface. The memory interface is designed to receive data signals (DQ) and a strobe signal (DQS) from a memory integrated circuit. The memory interface provides the data signals and strobe signal to the core circuitry of the FPGA.
Each of two input pins in the memory interface of the FPGA can be used to receive one single-ended data signal (DQ) or to receive one of two signals that embody a differential strobe signal (DQS). The memory interface includes two single-ended input buffers and a differential input buffer that are compliant with the SSTL (Stub Series Terminated Logic) and HSTL (High-Speed Transceiver Logic) standards.
The first input pin in the memory interface is coupled to an input of the first single-ended input buffer and to a first input of the differential input buffer. The second input pin in the memory interface is coupled to an input of the second single-ended input buffer and to a second input of the differential input buffer. If the input pins in the memory interface receive two single-ended data signals, the single-ended input buffers buffer the single-ended data signals. If the input pins in the memory interface receive a differential strobe signal, the differential input buffer buffers the differential strobe signal.